This disclosure relates generally to a pseudo SRAM device, and, more specifically, to a precharge control circuit of a pseudo SRAM, wherein a precharge signal can be generated when a chip select signal is disabled.
A random access memory (RAM) is a memory to store data within memory cells, and can be classified into a static RAM (SRAM) and a dynamic RAM (DRAM). SRAM cells have a static latching structure (including six transistors, or four transistors and two resistors), wherein data can be stored indefinitely while being applied with power. DRAM cells have a structure of one capacitor and one access transistor.
The pseudo SRAM is known to be a memory that internally automatically performs a refresh operation on memory cells without external control and has a similar interface and operational timing as those of SRAM in terms of its function, while having cells composed of one access transistor and one capacitor in the same manner as DRAM cells. The pseudo SRAM adopts DRAM cells, and thus includes a refresh related circuit, which was not adopted in existing SRAM. In the pseudo SRAM, data is stored as electric charges are accumulated on a capacitor, but may be lost because initial charges stored can be lost due to various causes such as leakage current. In order to prevent this, it is required that data within the memory cell be read before the data are lost, and the memory cell be re-charged with initial charges according to read information.
The read operation of the pseudo SRAM is performed as follows. If an address corresponding to a memory cell to be read is applied, it is input to a predecoder through an address buffer. At this time, an address transition detecting (ATD) circuit that senses variation in the address operates to generate an address shift detection signal ATD. The ATD circuit drives a word line driver through a row decoder in order to select a word line after predecoding, and then selects the selected word line. In a similar manner, if a column line corresponding to a selected memory cell is selected, the memory cell is selected. Data of the selected cell is input to a sense amplifier through a bit line. The data amplified in the sense amplifier are output to an output terminal through an output buffer.
The write operation of the pseudo SRAM proceeds as follows. A process of selecting a memory cell is the same as that of the read operation. Data input to an I/O pad is transmitted to a bit line connected to a memory cell to be written, and then input to a selected memory cell. Thereby, the write operation is completed.
The pseudo SRAM performs precharge if switching from an active mode such as the read or write operation to a standby mode, thus preparing for a next active mode. The pseudo SRAM produces a pulse signal for precharge through a precharge control circuit, and thus performing precharge.
In the conventional pseudo SRAM, however, if a write enable signal /WE is disabled or a disable pulse CS_P of a chip select signal /CS is generated in a period where an active signal NATV_LEVEL generated by address shift is low, the pulse signal is not recognized as a precharge command.
Furthermore, if all addresses becomes a high level when the chip select signal /CS shifts from a high level to a low level in a short period of time, the address shift detection signal ATD is not generated although the chip select signal /CS shifts from a high level to a low level.
As a result, an active operation for addresses all of which are high is not guaranteed since an active operation is performed without precharge.